Signal Extension
Retimers, active cables, and interconnect modules that hold signal integrity across boards, risers, and racks.
Retimers, active cables, and interconnect modules that hold signal integrity across boards, risers, and racks.
CXL memory expansion and high-radix switch boards that flatten the scale-up network and grow addressable memory.
Backplanes, trays, and management firmware that turn boards into a deployable, instrumented rack-scale pod.
Every product is engineered to be manufacturable, thermally-validated, and instrumented from the board up.
Standard-slot add-in and riser cards built around leading retimer silicon, with full signal-integrity validation and on-board telemetry so every link closes.
E3.S and add-in-card memory expanders and pooling boards that attach terabytes of fabric-addressable memory to hosts for expansion and disaggregation.
Active electrical and optical cable end-modules and network-adapter carriers for multi-rack GPU clustering, engineered for margin at 200G+ per lane.
High-radix PCIe, Ethernet, and scale-up switch line-cards and fabric trays with hot-swap serviceability and managed telemetry throughout.
Orthogonal and midplane backplanes plus optical-carrier trays that connect racks of accelerators into a coherent scale-up pod — the passive-and-active spine.
BMC-integrated telemetry, link bring-up, and diagnostics firmware that ships with every Betelgeuse board so operators can see and manage the fabric live.
PCIe Gen 6 / CXL 3.x reach extension in a standard slot, SI-validated and instrumented out of the box.
Request the product briefRecovers and re-transmits high-speed signals to roughly triple link reach across boards, risers, and cables.
Per-lane eye, error, and link-state metrics exposed over the BMC via Meissa firmware.
Standard CEM add-in card and riser variants that fit existing chassis without redesign.
| Series | Interface | Lanes | Form factor | Reach |
|---|---|---|---|---|
| Rigel R6-x8 | PCIe 6.0 / CXL 3.x | 8 | HHHL add-in card | ~3x baseline |
| Rigel R6-x16 | PCIe 6.0 / CXL 3.x | 16 | FHHL add-in card | ~3x baseline |
| Rigel R6-Riser | PCIe 6.0 | 16 | Riser / booster | Intra-chassis |
| Part number | Series | Interface | Lanes | Form factor |
|---|---|---|---|---|
| BLG-RGL-R6-0801 | R6-x8 | PCIe 6.0 / CXL 3.x | 8 | HHHL |
| BLG-RGL-R6-1601 | R6-x16 | PCIe 6.0 / CXL 3.x | 16 | FHHL |
| BLG-RGL-R6-16RS | R6-Riser | PCIe 6.0 | 16 | Riser |
Part numbers and specifications are provisional for V0.0.1 and subject to change before general availability.
Hold link margin between accelerators across a multi-slot server.
Extend PCIe/CXL over active cable into an adjacent rack.
Attach pooled CXL memory to hosts without latency penalties.
De-risk high-radix fabric boards with instrumented links.
Tell us the silicon and the form factor. We’ll tell you what it takes to ship it.
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