Signal integrity
Insertion-loss recovery, jitter, and eye margin across PAM4 lanes as rates climb from 112G toward 224G.
Research
Retimer integration, done to spec.
Betelgeuse Labs studies how DSP retimers are applied to high-speed interconnect boards — and why building them in accordance with the governing form-factor and signaling specifications is what keeps a link within compliance.
As channels shorten and per-lane rates rise, the retimer — with clock-and-data recovery, equalization, and reach extension — is often what stands between a marginal channel and a compliant one. Our research centers on applying retimer cards in accordance with the specifications that govern them, rather than treating signal integrity as an afterthought.
Built to the OSFP and QSFP-DD form factors and to the OIF CEI-224G electrical interface, a retimer is not an add-on. It is what allows host and module to interoperate at PAM4 rates that a passive channel can no longer carry on its own.
Built to spec
Work carried out against the OSFP and QSFP-DD form factors, OIF CEI-224G electrical interfaces, and PCIe and Ethernet signaling standards.
Reach & interoperability
Retimer, redriver, and clock-and-data recovery applied to keep host and module link stable and in compliance.
Governing standards & terms
- OSFP
- QSFP-DD
- OIF CEI-224G
- PAM4
- Retimer
- DSP
- CDR
- SerDes
- PCIe 6.x
- IEEE 802.3
- Signal Integrity
- Reach Extension
The silicon sets the ceiling. The board, built to spec, decides whether you reach it.