Rigel retimer add-in cards, now sampling
PCIe Gen 6 / CXL 3.x reach extension in a standard slot — SI-validated and instrumented out of the box.
See the family →Best-in-class silicon, made deployable
We integrate leading connectivity silicon so you get the right part for the workload — without running a silicon program of your own.
Our approach → Portfolio
Boards for every link in the fabric
Three problem areas, one integration discipline — from signal extension to full rack systems.
Signal Extension
Retimers, active cables, and interconnect modules that hold signal integrity across boards, risers, and racks.
Memory & Fabric
CXL memory expansion and high-radix switch boards that flatten the scale-up network and grow addressable memory.
Rack Systems
Backplanes, trays, and management firmware that turn boards into a deployable, instrumented rack-scale pod.
Hardware + software
Every board ships instrumented
Meissa firmware brings BMC-integrated telemetry, link bring-up, and diagnostics to every design — so the fabric is observable and manageable the day it lands in the rack.
Meet Meissa → Signal integrity
The board is the performance
At 64 GT/s the datasheet is only a starting point. Our materials, stack-up, and layout discipline are what turn silicon capability into a link that actually closes at scale.
Inside the engineering → Our thesis
AI clusters are bottlenecked by interconnect, not compute.
Everyone sells silicon into that bottleneck. Almost no one builds open-market boards and systems around it. That seam — between the chip and the rack — is where Betelgeuse Labs lives.
Why we exist Interop-first
Validated against the silicon vendors’ own ecosystems
We test every design for standards compliance — PCIe-SIG CEM, OCP, E3.S, OAM — so your fabric stays interoperable and future-proof.
PCIe CEMCXLEthernetE3.SOCPOAM
Insights
From the lab
Notes on signal integrity, interconnect, and building deployable AI hardware.
Engineering
Why the board decides whether a PCIe Gen 6 link closes
Signal integrity at 64 GT/s is a materials-and-layout problem long before it is a silicon problem.
Read more →Perspective
The interconnect is the bottleneck, not the compute
AI clusters now stall on how fast accelerators can talk — which is exactly where a board partner adds value.
Read more →Product
Designing CXL memory boards for pooling at rack scale
What it takes to attach terabytes of fabric-addressable memory without wrecking latency.
Read more →Build the hardware behind AI
We’re a small team of board, signal-integrity, and systems engineers. If turning the newest connectivity silicon into shipping product sounds like your kind of problem, let’s talk.
Silicon-agnostic by design
We integrate the right connectivity silicon for each workload, so you are never locked to a single vendor’s roadmap.
Signal integrity is the product
At 200G+ per lane and PCIe Gen 6, the board is the performance. Our SI/PI engineering turns a datasheet into a link that actually closes.
Rack-ready, not reference-only
Manufacturable, thermally-validated, standards-compliant hardware — from schematic to volume, not lab curiosities.